1. Field of the Invention
The present invention generally relates to electronic design automation. More specifically, the present invention relates to techniques and systems for optimizing a circuit design during a logic design stage to reduce routing congestion during a placement and routing stage.
2. Related Art
Performing a routing operation on a circuit design's netlist is an expensive process which can take several days to complete. To make matters worse, the routing operation is not always guaranteed to succeed. In some situations, standard cell routing does not succeed because a region of the microchip does not have sufficient wiring resources for routing the signal interconnections that exist in that region. This situation is typically known as routing congestion.
Routing congestion is often mitigated by using a cell placement algorithm to complement a routing operation, and produce an optimized physical implementation from the netlist of a circuit design. This placement algorithm attempts to spread out standard cells in areas of the physical implementation where the algorithm believes that congestion will occur. However, many cases still exist where the placement algorithm cannot resolve every congestion issue on the physical implementation.